1. Field of the Invention
The present invention relates in general to integrated circuit testers and in particular to a tester employing a salphasic plane when self-calibrating its signal timing.
2. Description of Related Art
A typical integrated circuit tester tests a digital logic integrated circuit device under test (DUT) by applying test signals of various logic states to DUT input terminals and by monitoring states of signals produced at DUT output terminals in response to the test signals to determine whether the DUT is behaving as expected. Such a tester typically includes a set of tester channels, each connected to a separate terminal of the DUT, and each carrying out all test activities with respect to that DUT terminal. A test is typically organized into a succession of test cycles. Each channel receives input ACTION and TIMING data for each test cycle telling the channel what actions to take during the test cycle and indicating the times during the test cycle at which it is to take those actions. Each channel may also receive EXPECT data indicating expected states of the DUT output signal (if any) during the test cycle. A channel may carry out any one or more of several actions during a test cycle. Such actions include driving a test signal applied to the DUT terminal to a high or low logic state, tristating the test signal, or sampling a DUT output signal to determine its logic state and comparing it to the EXPECT data.
Each channel includes a tristate driver for supplying a test signal to the DUT terminal and a compare circuit for producing output data indicating the state of the DUT output signal produced at the DUT terminal. A formatting and timing circuit within each channel responds to the input ACTION and TIMING data by producing three control signals, "TRISTATE", "DRIVE" and "COMPARE". The TRISTATE signal tristates the channel's driver and the DRIVE signal indicates whether the driver's output test signal is to be of a high or low logic level. The COMPARE signal tells the compare circuit when to sample the state of the DUT output signal. The ACTION data input to the formatting and timing circuit indicates which of the DRIVE, TRISTATE, and COMPARE signals are to change state during a next test cycle while the TIMING data indicates times during the test cycle at which those state changes are to occur.
In order to properly test a DUT it is necessary to closely synchronize the various test activities of all tester channels. For example suppose a DUT is expected to produce a high logic level output signal at a DUT terminal B 10 nanoseconds after it receives a high logic level test signal at a DUT terminal A at some time T.sub.x relative to the start of a test. To test the DUT for this expected behavior a first tester channel accessing DUT terminal A must assert its DRIVE signal so as to cause the channel's driver to send a high logic level signal to terminal A at time T.sub.x. Later a second tester channel accessing DUT terminal B must assert its COMPARE signal to initiate sampling of the second channel's compare circuit so as to acquire data indicating the state of the DUT output signal at terminal B at time T.sub.x +10 nsec.
Since we want the test signal to arrive at terminal A at time T.sub.x, the timing and formatting circuit accessing terminal A must assert its output DRIVE signal some time before time T.sub.x in order to allow the driver time to respond to the DRIVE signal by changing the state of its output test signal and in order to allow the test signal sufficient time to travel to the DUT terminal. Thus while the ACTION and TIMING data input to the timing and formatting circuit may indicate the test signal is to be driven high at time T.sub.x, the timing and formatting circuit should be "calibrated" to take the necessary action of asserting the DRIVE signal with an appropriate lead time before time T.sub.x. That lead time should equal the total signal path delay between the DRIVE signal input to the driver and the DUT terminal.
Conversely, although the ACTION and TIMING data input to the second tester channel indicates that the channel is to sample the DUT output signal at time T.sub.x +10 nanoseconds, the timing and formatting circuit of that channel must take its necessary action of asserting the COMPARE signal input to the compare circuit at some time other than T.sub.x +10 nanoseconds in order to allow the DUT output signal sufficient time to travel to the compare circuit and to allow for the compare circuit time to respond to the COMPARE signal to sample it.
Thus in order to accurately time events at the DUT terminals, the timing and formatting circuit within each channel must advance state changes in their DRIVE and TRISTATE output signals and delay state changes in their COMPARE output signals from the times indicated by their input TIMING data to account for the above-described signal path delays. Since the drive and compare signal path delays can vary from channel-to-channel it is necessary to separately measure those signal path delays for each channel so that its timing and formatting circuit can be separately calibrated. Unfortunately measuring those signal path delays, typically through the use of oscilloscopes or other timing measurement devices, has heretofore been a difficult, tedious and timing consuming manual process.
What is needed is a system for quickly and easily calibrating the timing of an integrated circuit tester.